The present invention relates generally to an apparatus and method for synchronizing signals between asynchronous clock domains within digital electronic circuits, and more particularly, to decoupling asynchronous clocks within different clock domains in ultra low power real time clock (RTC) applications within battery operated system on chip (SoC) applications.
SoC devices include components and devices that contain different memories and modules that have different cycle times. Different methods have been adopted for data and clock synchronization within such systems. However, these methods and systems tend to be power and space inefficient. In particular with SoC devices having battery back-up assisted RTC applications, the amount of power consumed is a concern and should be reduced or minimized. Of all the peripherals and components of the SoC, RTC devices are kept operational with a battery supply even when the main power is turned off. The RTC devices are kept operational to maintain vital functions such time keeping. RTC devices also may perform other operations when the main power is turned off, such as critical data storage, device tamper detection and clock compensation. It is necessary for these functions to remain operational when the main power to the SoC is removed. For example, in some applications, such as in utility metering and medical applications, the RTC implementations are required to work for 15-20 years on a single battery. RTC devices are thus designed to consume the least amount of power possible.
RTC implementations use at least two clocks with different clock speeds in different clock domains. The two clocks typically form a fast clock domain for the register programming interface and a slow clock domain for maintaining time and date functionality. The two clocks are typically completely asynchronous to each other; however, signals are required to be transmitted between these clock domains, and thus these systems are prone to meta-stability states and missed signals from the fast to the slow clock domains.
In conventional clock and data synchronization systems, handshake circuits and synchronizers, respectively, are used. Typically, two to three flip-flops are used in conventional synchronizer design. This requires the data on the fast clock domain, i.e. the load value and the enable signal, to be kept constant or stable until the slower clock domain samples the data. Each flip-flop consumes power when kept in the constant or stable state. Accordingly, as the number of flip-flops increases when larger and multiple bit values are to be transferred, the area and power consumption also is increased. Additionally, these synchronizers require the clock to be available all the time, which further increases power consumption even when no registers are being accessed. A typical synchronization circuit used in conventional RTC devices is shown in FIGS. 1 and 2.
Therefore, it is desirable to have more efficient methods and systems to reduce power consumption of asynchronous clocks in systems with different clock domains.